pi74fct373t/533t/573t (25 w w w w w series) p174fct2373t/2573t octal transparent latches 1 ps2015a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct373/2373t and pi74fct573/2573t logic block diagram pi74fct533t logic block diagram product description: pericom semiconductors pi74fct series of logic circuits are produced in the companys advanced 0.6/0.8 micron cmos technology, achieving industry leading speed grades. all pi74fct2xxx devices have a built-in 25 ohm series resistor on all outputs to reduce noise resulting from reflections, thus eliminating the need for an external terminating resistor. the pi74fct373t/533t/573t and p174fct2373t/2573t are 8-bit wide octal transparent latches designed with 3-state outputs and are intended for bus oriented applications. when latch enable (le) is high, the flip-flops appear transparent to the data. the data that meets the set-up time when le is low is latched. when oe is high, the bus output is in the high impedance state. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct373t/533t/573t (25 w w w w w series) p174fct2373t/2573t octal transparent latches fast cmos octal transparent latches product features: ? pi74fct373/533/573/2373/2573t is pin compatible with bipolar fast? series at a higher speed and lower power consumption ?25 w series resistor on all outputs (fct2xxx only) ? ttl input and output levels ? low ground bounce outputs ? extremely low static power ? hysteresis on all inputs ? industrial operating temperature range: C40c to +85c ? packages available: C 20-pin 173 mil wide plastic tssop (l) C 20-pin 300 mil wide plastic dip (p) C 20-pin 150 mil wide plastic qsop (q) C 20-pin 150 mil wide plastic tqsop (r) C 20-pin 300 mil wide plastic soic (s) ? device models available upon request o d g oe le d 0 o 0 o d g d 1 o 1 o d g d 2 o 2 o d g d 3 o 3 o d g d 4 o 4 o d g d 5 o 5 o d g d 6 o 6 o d g d 7 o 7 o d g oe le d 0 o 0 o d g d 1 o 1 o d g d 2 o 2 o d g d 3 o 3 o d g d 4 o 4 o d g d 5 o 5 o d g d 6 o 6 o d g d 7 o 7
pi74fct373t/533t/573t (25 w w w w w series) p174fct2373t/2573t octal transparent latches 2 ps2015a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 inputs outputs d n le oe o n hhll lhlh xxhz pi74fct533t truth table (1) inputs outputs d n le oe o n hhlh lhll xxhz pi74fct373/573/2373/2573t truth table (1) 1. h = high voltage level l = low voltage level x = dont care z = high impedance pin name description oe output enable input (active low) le latch enable input (active high) d 0 -d 7 data inputs o 0 -o 7 3-state outputs o 0 -o 7 complementary 3-state outputs gnd ground v cc power product pin description pi74fct373/2373t product pin configuration pi74fct533t product pin configuration pi74fct573/2573t product pin configuration 20-pin l20 p20 q20 r20 s20 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe o 0 d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd vcc o 7 d 7 d 6 o 6 o 5 d 5 d 4 o 4 le 20-pin l20 p20 q20 r20 s20 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe o 0 d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd vcc o 7 d 7 d 6 o 6 o 5 d 5 d 4 o 4 le 20-pin l20 p20 q20 r20 s20 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd vcc o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 le
pi74fct373t/533t/573t (25 w w w w w series) p174fct2373t/2573t octal transparent latches 3 ps2015a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ................................................................. C65c to +150c ambient temperature with power applied ................................. -40c to +85c supply voltage to ground potential (inputs & vcc only) .......... C0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ....... C0.5v to +7.0v dc input voltage ......................................................................... C0.5v to +7.0v dc output current ................................................................................... 120 ma power dissipation ......................................................................................... 0.5w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 5.0v 5%) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = C15.0 ma 2.4 3.0 v v ol output low current v cc = min., v in = v ih or v il i ol = 64 ma 0.3 0.55 v v ol output low current v cc = min., v in = v ih or v il i ol = 12 ma (25 w series) 0.3 0.50 v v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v cc = max. v in = v cc 1a i il input low current v cc = max. v in = gnd C1 a i ozh high impedance v cc = m ax .v out = 2.7v 1 a i ozl output current v out = 0.5v C1 a v ik clamp diode voltage v cc = min., i in = C18 ma C0.7 C1.2 v i off power down disable v cc = gnd, v out = 4.5v 100 a i os short circuit current v cc = max. (3) , v out = gnd C60 C120 ma v h input hysteresis 200 mv capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ max. units c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested.
pi74fct373t/533t/573t (25 w w w w w series) p174fct2373t/2573t octal transparent latches 4 ps2015a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.1 500 a supply current d i cc supply current per v cc = max., v in = 3.4v (3) 0.5 2.0 ma input @ ttl high i ccd supply current per v cc = max., v in = v cc 0.15 0.25 ma/ input per mhz (4) outputs open v in = gnd mhz oe = gnd le = v cc one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 1.5 3.0 (5) ma current (6) outputs open v in = gnd f i = 10 mh z 50% duty cycle oe = gnd v in = 3.4v 1.8 4.5 (5) le = v cc v in = gnd one bit toggling v cc = max., v in = v cc 3.0 6.0 (5) outputs open v in = gnd f i = 2.5 mh z 50% duty cycle oe = gnd v in = 3.4v 5.0 14.0 (5) le = v cc v in = gnd eight bits toggling notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i ni) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
pi74fct373t/533t/573t (25 w w w w w series) p174fct2373t/2573t octal transparent latches 5 ps2015a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct373/2373t switching characteristics over operating range 373t/2373t 373at/2373at 373ct/2373ct 373dt com. com. com. com. parameters description conditions (1) min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 8.0 1.5 5.2 1.5 4.2 1.5 3.8 ns t phl d n to o n r l = 500 w t plh propagation delay 2.0 13.0 2.0 8.5 2.0 5.5 1.5 4.9 ns t phl le to o n t pzh output enable time 1.5 12.0 1.5 6.5 1.5 5.5 1.5 5.5 ns t pzl oe to o n t phz output disable time (3) 1.5 7.5 1.5 5.5 1.5 5.0 1.5 5.0 ns t plz oe to o n t su setup time high or 2.0 2.0 2.0 2.0 ns low, d n to le t h hold time high or 1.5 1.5 1.5 1.5 ns low, d n to le t w le pulse width (3) 6.0 5.0 5.0 4.0 ns high pi74fct533t switching characteristics over operating range 533t 533at 533ct com. com. com. parameters description conditions (1) min max min max min max unit t plh propagation delay c l = 50 pf 1.5 10.0 1.5 5.2 1.5 4.2 ns t phl d n to o n r l = 500 w t plh propagation delay 2.0 13.0 2.0 8.5 2.0 5.5 ns t phl le to o n t pzh output enable time 1.5 11.0 1.5 6.5 1.5 5.5 ns t pzl oe to o n t phz output disable time (3) 1.5 7.0 1.5 5.5 1.5 5.0 ns t plz oe to o n t su setup time high or 2.0 2.0 2.0 ns low, d n to le t h hold time high or 1.5 1.5 1.5 ns low, d n to le t w le pulse width (3) 6.0 5.0 5.0 ns high notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter guaranteed but not production tested.
pi74fct373t/533t/573t (25 w w w w w series) p174fct2373t/2573t octal transparent latches 6 ps2015a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter guaranteed but not production tested. pi74fct573/2573t switching characteristics over operating range 573t/2573t 573at/2573at 573ct 573dt com. com. com. com. parameters description conditions (1) min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 8.0 1.5 5.2 1.5 4.2 1.5 3.8 ns t phl d n to o n r l = 500 w t plh propagation delay 2.0 12.0 2.0 8.5 2.0 5.5 2.0 4.9 ns t phl le to o n t pzh output enable time 1.5 9.5 1.5 6.5 1.5 5.5 1.5 5.5 ns t pzl oe to o n t phz output disable time (3) 1.5 6.5 1.5 5.5 1.5 5.0 1.5 5.0 ns t plz oe to o n t su setup time high or 2.0 2.0 2.0 1.5 ns low, d n to le t h hold time high or 1.5 1.5 1.5 1.0 ns low, d n to le t w le pulse width (3) 6.0 5.0 5.0 3.0 ns high pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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